文黑网 -文档下载

教育部卓越计画通信及网路技术

.
教育部卓越计画通信及网路技术
WBWB--CDMACDMA系统研制简介系统研制简介
报告人:邓俊宏
日期:90年4月25日
.
2
内内容容
1.1.CSIST WCSIST W--CDMA CDMA 系统研制简介系统研制简介
2. W2. W--CDMA CDMA 智慧型天线系统简介智慧型天线系统简介
3. 3. 本实验室本实验室WW--CDMACDMA研究进度现况研究进度现况
.
3
1.1.CSIST WCSIST W--CDMA CDMA 系统研制简介系统研制简介
.
4
WW--CDMACDMA下链路验证系统组成下链路验证系统组成
ADPCM
Decoder
W-CDMA
BasebandModule
Inner Receiver
A/D
A/D
Viterbi Soft
Decoder
(K=9; r=1/2)
用户台
RF/IF模组雏型
AptixMP4接收单元
用户台基频接收模组Synthesizer 1
(HP 8665A)
Synthesizer 2
(HP 8665A)
LO#1
(1772.5 MHz)
LO#2
(380 MHz)
AGC Control
ADPCM
Encoder
Frame
Process
RRC
RRC
D/A
D/A
OR
Rode & Schwartz
SMIQ03AptixMP4
发射单元
基地台基频发射模组
LPA
(28 dBm)
Multipath
Emulator
(NoiseCom
MP 2700)
Synthesizer
基地台
Up-Converter
1962.5 MHz
Audio Source
现有仪器装备自行设计模组
.
5
WW--CDMACDMA下链路验证系统架构下链路验证系统架构
(Next Stage)(Next Stage)
Multipath
Emulator
(NoiseComm
MP 2700)
3GPP W-CDMA
Signal Generator
(R&S SMIQ)
)(
~
tbTPC
command
Power Increased
Due to PC
System
Controller
CN Generator
(Interference &
Jamming)
(TAS 4600)
)(tb
LPA
BER
S.S. W-CDMA
Baseband
Module
S.S.
Antenna Module
S.S. W-CDMA
RF/IF Module
自制装备
.
6
基频模组设计方法基频模组设计方法
EDA Tools
Algorithms Design
(Floating and Fixed Point)
Architecture
Optimization
HW/SW
Implementation
Integration Test
BasebandChipsets/Modules
Design Flow
FPGA = Field Programmable Gate Array
VA = Visual Architect
HDS = Hardware Design System
B2 Spec.
C2 Spec.
VA and HDS
(Cadence)
VLSI
Development
Prototype
Verification
System
(AptixMP4)
DSP
(TI C54x)
FPGAASICDSP P
Module
SPW
(Cadence)
P Developing
System
SDL
(Verilog
/TeleLogic)
Protocol
Stack
VerilogSimulator
(Cadence)
Included in the current demonstration
.
7
DPDCH
data
300 bits
Ad
d
tail
8
bits
C
onv
olut
ional
Co
de
R
=
1/
2,
K
=
9
30
8
bits
Ra
te
M
atchi
ng
616
bits
16
pu
nc
tured
er
ase 3
8th d
ata600
bits
Bl
ock
In
terleaving
40
×
15
BC
CH
4b
its
6b
its
Pi
lot
dat
a
Ti
m
e
M
ux
10
bits/slot
15
kbps
C
ch
,25
I,Q
Di
gital
Sum
BA
3.
84
M
cps
Csc
ra
m
ble
3.84
M
cps
64
PN
Co
de
4
SCH
On
ce
Pe
r F
ram
e
64
ch
ips
inpu
t
se
lector
Te
st
patern
300bit
s /
fram
e
PN
9 test sequen
ce
free r
unni
ng
ADP
C
M
e
ncoded
dat
a
3.
84
M
cps
P
N
15 t
est sequence
free r
unni
ng
WW
--CDMA CDMA
系统传输格式系统传输格式
.
8
发射单元实体发射单元实体
.
9
雏型连测示意图雏型连测示意图
.
10
RF & IFRF & IF模组雏型方块图模组雏型方块图
Rx
A
n
tenna
BP
F
N.F
. =
8 dB
(T
py
.)
Outdoor
Unit
Cable
B.W
:
1930-
1990 MHz
LN
A
R
F
9957
AGC
379.904MHz
B.W
:
1850-
1910 MHz
1962.496MHz
P
LL ICPL
L
I
C
1882.624MHz
LN
A
Mix
er
SAW
RF99
36
Down
C
onve
rter
3
79.904MHzAG
C
RF9
958
Mix
er
SA
W
BPF
DriveAmp.
Upconve
rte
r
Tx
Ante
nna
Cable
Ce
ramic
BP
F
P1
dB
28.5 dB
mBP
F
Pout:8 dB
m(
Tpy
.)
DriverAmp.
RF
2310
P.A.
BP
F
.
11
RF & IFRF & IF模组雏型实体图模组雏型实体图
.
12
基频接收模组雏型方块图基频接收模组雏型方块图
RRC
RRC
Synchronizer
(Xilinx4085XL)
Complex
Multiplier
Searcher
(Xilinx40150XV)
Channel
Estimator 3
Channel
Estimator 2
Channel
Estimator 1
RAKE
Finger 1
MRC
(Xilinx
4085XL)
Parallel-to-serial
/De-Interleaver
/De-Ratematching
Clock
Recovery
AFC
(Xilinx
40150XV)
W-CDMA
BasebandModule
Inner Receiver
AGC
(Xilinx
4028EX)
RAKE Combiner
RAKE
Combiner
SIR
Measurement
2
3
TPC
Command
Target SIR
Downlink Frame
Format Generator
(Xilinx4085XL)
AD 9042
A/D
From
Analog Interface
A/D
AD 9042
To IF AGC
ADPCM
Control
Viterbi Soft Decoder
(K=9, r=1/2)
(Xilinx4062XL)
ADPCM
Decoder
(Winbond
W9001)
Speaker
Total Gate Counts: ~412,600
.
13
RootRoot--RaisedRaised--CosineCosine滤波器电路功能方块图滤波器电路功能方块图
4
Tc
Z

4
Tc
Z

4
Tc
Z

4
Tc
Z
...
∑
C0
...
...C1C2C33
.
14
AGCAGC及及DCDC--OffsetOffset补偿电路功能方块图补偿电路功能方块图
RX
filter
image
filter
IF
SAWPDQuad
LP
LP
A/D
A/D
RC
filter
RC
filter
mean
mean
anti-aliasing
filter
Dersodulator
AGC
Cable
LNA/mixer
IQ
to
Complex
RC filter
Digital Circuit
I
Q
Vref
×
1
Z
SIR compensation
PDM gen.
0C2
Loop filter
.
15
Synchronizer Synchronizer 电路功能方块图电路功能方块图
自测电路
PN
C
ode
Match
ed F
ilter
PN
C
ode
Match
ed F
ilter
(
)
2
(
)2
Fi
nd
同步器电路
自测参数
Si
gna
l from
I-C
hannel
R
R
C

Fi
lter
Si
gna
l from
Q
-Ch
an
nel
RRC
F
ilter
F
rame S
S
ignal Generator
) (
.
16
Searcher Searcher 电路功能方块图电路功能方块图
Frame Start Time
Sc
ram
ble
Co
de
Ge
nerator
D
espread
er
En
velop
D
etect
or
D
ela
y Profile
M
em
o
Ti
m
ing
Co
ntrol
R/
W
A
ddress
Ge
nerator
I
STER
Y
Q
.
17
Clock Recovery Clock Recovery 电路功能方块图电路功能方块图
FMA
X
64
Ze
roing
P
rof
ile input

fro
m
S
earch
er
M
a
x. Fi
nder
Devi
at
ion
F
inde
rFi
nger
Finder
Ma
x. Va
lue
M
ax.
Inde
x
0
63
32
16
48
8
244
05
6
0
63
32
16
48
8
244
05
6
0
63
32
16
48
8
244
05
6
MA
X
_F
S
T
MA
X
_S
E
C
M
AX_
T
R
D
设为
0
设为
0
S
tep1:
S
tep2:
S
tep3:
.
18
RAKE ReceiverRAKE Receiver电路功能方块图电路功能方块图
average
arg ( )
BCCHCodegen
delayalign
∫

1
0
SF
WMSA
∫10230
Tslot
( )*
timealign
Freq Discriminator
channel estimate
TimealignCodegen
i
i
^
,
T
pathI,Q
finger1
finger3
finger2
d2d1d3
i
i
^
,
T
path
1er2r3r
(from searcher)
.
19
AFCAFC电路功能方块图电路功能方块图
co
m
p
lex
toIQ
Ma
xira
t
co
m
phacom
BCC
H
Co
dege
n
de
lay
alig
n
WMSA
∫10
23
0
ti
m
e
alig
n
phase
e
sti
m
ate
Ti
me
alig
n
Co
de
ge
n
I,
Q
fin
g
er1
fi
n
g
er3
fi
n
g
er2
d2d1d3
to
r
ece
iv
er
Z
-1
L
ook
-u
p
ta
b
le
2T
C2
Lo
o
p
F
ilter
( )
*
NC
O
freq_i
n
itial
to tr
an
sm
tte
r
RR
C
to
DTCXO
Ts
lo
t
( )
*
RR
C
θ

θ
θj
e
1
1
φje
r
2
2
φje
r
3
3
φje
r
iiTpath
^
,
.
20
通道解码器前之正规化电路功能方块图通道解码器前之正规化电路功能方块图
Ra
ke
Co
m
biner
Down
-sampl
e
1 s
lot
Repea
t
1 s
lot
x
yx
()∫
+
++
sl
ot
sl
ot
T
i
iT
N
1
1
ττ
Norm
.
21
SIR MeasurementSIR Measurement电路功能方块图电路功能方块图

0
0
0

1+
j
1 α
α
Tslo
t
Z
2
1
∑

m
N
()
finge
r2
finge
r3
)
(k
A
)
(k
B
channe
l
estima
te
()k
ej
1
1
^
^
1
ε
α
θ
=
fi
ng
er1
)
(
~
=
k
I
expone
nti
al filter
()k
I
es
I/P
2
2^
k
ε
()
2
1^
k
ε
()
2
3^
k
ε
Es
tim
ate I
.
22
FPGAFPGA通通用模组用模组电路实体图电路实体图
.
23
基频接收模组各基频接收模组各FPGAFPGA暨模组位置图暨模组位置图
FUNCTION STATUS
I CH A/D
RRC
Q CH A/D
ADPCM CODEC/AGC
VITERBI DECODER
ADPCM CODEC
FRAME PROCESS
CLK RECOVERY
AFC
RAKE
.
24
2. W2. W--CDMA CDMA 智慧型天线系统简介智慧型天线系统简介
.
25
SectorizedSectorizedSmart Antenna System Smart Antenna System 实体示意图实体示意图
.
26
SectorizedSectorizedSmart Antenna System Smart Antenna System 基本设备图基本设备图
.
27
Single Channel Digital Down Converter Single Channel Digital Down Converter 方块图方块图
.
28
MultiMulti--channel Wideband Digital Radio channel Wideband Digital Radio 方块图方块图
.
29
SectorizedSectorizedSmart AntennaSmart Antenna基基频接收机功能方块图频接收机功能方块图
To deinterleaver
and
decoder
RF/IF
Down
Converter
A/D
A/D
A/D
A/D
IF/
Baseband
Digital
Down
Converter
Fixed
Multiple
Beamformer
(FFT)
Sectorα
RF/IF
Down
Converter
A/D
A/D
A/D
A/D
IF/
Baseband
Digital
Down
Converter
Fixed
Multiple
Beamformer
(FFT)
Sectorβ
RF/IF
Down
Converter
A/D
A/D
A/D
A/D
IF/
Baseband
Digital
Down
Converter
Fixed
Multiple
Beamformer
(FFT)
Sectorγ
Beam
Selection
or
Weight
Combiner
(software)
Data
Demodulator
for user k
Space-Time
MRC
Combiner
Switch controller
or
weight update
MRC : maximum ratio combiner
Figure 1 : Structure of software space-time smart antenna system
.
30
基频接收机后续待发展项目基频接收机后续待发展项目
运用FFT技术,执行fixed multiple beamformer功能.
执行adaptive weighted combiner (NLMS)功能,
适用於adaptive antenna systems.
执行switched beam controller and selection功能,
适用於switched beam systems.
.
31
2.2.本实验室本实验室WW--CDMACDMA研究进度现况研究进度现况
.
32
实验室实验室WW--CDMACDMA研究进度规划研究进度规划
发射, 通道传输环境与量测设备建立(90.12.31)
单向链路W-CDMA 高速传输环境, Rake 接收与Power control 展示(91.06)
单向链路W-CDMA 智慧型天线展示(92.06)
Q3Q4Q1Q2Q3Q4Q4Q3Q2Q1
智慧型天
线展示
FY 92
12/31
Rake 接收
展示
FY 91FY 90
.
33
WW--CDMA CDMA 研究进度现况研究进度现况(1/3)(1/3)
发射, 通道传输环境与量测设备建立:
采购设备与分工:
-进行采购设备:
Rohde&Schwarz SMIQ.
Agilentdigital pattern generator,digital oscilloscope.
IntersilIF 4 channel digital down converter(DDC) EVM module, synthesizer, BPF
filter, SAW filter, A/D D/A module.
Antenna system.
-进行设备连结与测试:
谭钲筑先生:负责Agilentdigital pattern generator-> AptixMP3C D/A -> RS
SMIQ -> TxAntenna -> Rx Antenna -> IntersilRF module -> IntersilIF DDC
module -> AptixMP3C A/D -> Agilentdigital logical analyzer or oscilloscope.
.
34
WW--CDMA CDMA 研究进度现况研究进度现况(2/3)(2/3)
单向链路W-CDMA高速传输环境,Rake接收与Power control研究:
发展方法与分工:
-已具备,但持续精进部份
陈智源先生: 即将於90.6.30. 完成W-CDMA 基频关键技术VHDL模拟与实现.
-进行W-CDMA 基频关键技术,实现於XilinxFPGA 与AptixMP3C 雏型系统
黄照尧先生:负责TxFrame process, RRC, Synchronizer, Searcher, Clock recovery,
Rake combiner, Fast channel estimator.
林文祁先生:负责AFC, SIR measurement, Power control, Deinterleaver,
Deratematching, Viterbidecoder.
.
35
WW--CDMA CDMA 研究进度现况研究进度现况(3/3)(3/3)
单向链路W-CDMA 智慧型天线:
发展方法与分工:
-已具备,但持续精进部份
陈世芳先生: 即将於90.6.30. 完成W-CDMA Adaptive Antenna digital
beamformering关键技术TI C6201 模拟与实现.
陈世芳先生:持续进行W-CDMA Sector Switched beam 关键技术TI C6201 模拟
与实现.
-进行W-CDMA 基频关键技术,实现於XilinxFPGA 与AptixMP3C 雏型系统
黄照尧先生:负责Adaptive Antenna digital beamformering.
林文祁先生:负责Sector Switched beam .
.
36
结结论论
基於CSIST W-CDMA 研制经验, 结合实验室长期Smart antenna
研究成果, 再配合优秀的研究生群, 相信可以如期完成阶段性的研
究.
希望未来能结合Aptixsystem , DSP (TI or Lucent …) 与CPU
(ARM, Power PC, …) 等系统, 完成真正Soft Radio 可程式化快速
雏型发展系统, 参考下图:
.
37
AgilentAgilentARM Integrator DemoARM Integrator Demo
Lucent DSP EVMARM CPU Borad
.
38
ARM Integrator/AP AHB with AXHARM Integrator/AP AHB with AXH--ARMINTARMINT--1 I/O1 I/O
.
39
MP3CF with Lucent 16410 DSP moduleMP3CF with Lucent 16410 DSP module
.
40
Lucent 16410 DSP Evaluation BoardLucent 16410 DSP Evaluation Board

引用地址:http://www.wenhei.com/document/1198870/